1. Field of the Invention
The present invention relates to a switching matrix (also known as switching fabric) for a telecommunication network element, typically an ADM (Add/Drop Multiplexer) or a XDC (Cross-Data-Connect). In particular, the present invention relates to an improved memory based switching matrix for such a network element.
2. Description of the Prior Art
As it is known, an ADM is a network element that provides access to all, or some subsets, of the constituents signals contained within an STM-N. The constituent signals are added to or dropped from the STM-N signal as it passes through the ADM.
Digital cross-connect systems are commonly employed to controllably rearrange and redirect the contents of signals being communicated in digital transmission systems. However, with ever increasing demands for larger transmission capacity, there is a need for increasingly larger capacity non-blocking switch units used in the cross-connect switching fabric. In particular, there is the need to provide a fabric switch whose capacity can be easily varied.
The usual approach is the so-called “bit slice approach” in which the cross-connection is carried out on a number of layered matrices performing, in the most general case, a single bit based switching, namely a single bit-by-single bit cross connection. In such architecture, the incoming payload is distributed to the layered matrices and properly recombined at the output. Usually the data word is conveniently sliced in a fixed number of bits (1, 2, 4). Through such an approach, the switching capacity becomes increased but the provisioning of the matrices is still rather complicated.
The bit slice approach is based on the use of a number of random access memories (RAMs). Indeed, the basic element is a pair of RAMs of the same size. One RAM of the pair of RAMs is designed for storing the incoming data flows whilst the other one is designed for reading the switched output data (stored in the immediately previous step). The task of each of them changes when the RAM storing data is completed.
The ideal architecture is built with a pair of RAMs with as many reading ports as the number of output links. Usually, the maximum number of reading ports of a physical RAM is four. Thus, in order to realize a high capacity matrix switch a number of RAM pairs have to be used.
In the practical basic solution, one pair of RAMs generates one output flow, each RAM having a single reading port. The complete cross-connection of m*i input data flows is obtained using m*i pairs of RAMs. In other words, the basic solution provides for a pair of RAMs for each single outcoming flow, with each of the single RAMs having a single reading port, while all the incoming data are written.
This solution is applicable both for single port reading RAMs and for multi port reading RAMs: the number of output flows equals the number of reading ports. The number of RAM pairs is equal to the total number of the output flows divided by the number of reading ports: to cross-connect m*i flows using RAMs with n reading ports, m*i/n pairs of RAMS are needed. Each output flow is composed of data, which are read from a RAM according to the information address stored in the devoted registers that in turn are written by a microprocessor.
Profitably, this known memory-based arrangement can be used in a scalable (multi chip) architecture. In that case a microprocessor has to configure sequentially each of the chips.
As said above there is an increasing request to have a switching matrix able to manage a large number of backpanel flows, with each backpanel flow carrying a large number of tributaries in frame format. For instance, there could be the need to manage 64 backpanel flows in a TDM (Time Division Multiplexing) configuration, each of them carrying 384 tributaries formed, in turn of two bytes of 8 bits (one word is 16 bits in total).
With the known arrangement, for each incoming flow, the device would have to store 384 words for each tributary in a first RAM. When the step of storing the 384 words of the tributary has finished, further 384 words would be incoming and have to be stored in the RAM associated to the previous one. In the same time, the first RAM would be read and would become available for storing incoming data.
The problem under such a known memory based switch device is that it would request a large amount of memory due to the fact that inside each RAM all the input data are written and that for each output flow there are two RAMs. The required RAM is calculated by multiplying the number of bits for each tributary by the number of tributaries by the number of input links by the number of output links by 2 and divided by the number of reading ports (the multiplication by 2 is need because of there are both working and stand-by RAMs). If, for instance, the number of bits for each tributary is 16, the number of tributaries is 384, the number of input links is 64, the number of output links is 64 as well, and the number of reading ports is one, the required RAM is 50 Mbit (16×384×64×64×2/1). Presently, the maximum RAM which is conveniently implemented on an ASIC device is about 15 Mbit. Therefore, such a RAM would not be conveniently implemented in a single ASIC and thus a switching matrix complying with the above requirement is not available.
In principle, the number of reading ports could be increased by reading the RAMs at a frequency higher than the writing frequency. For instance, if the writing frequency is 155.5 MHz, the reading frequency could be double (311 MHz). In this way, the number of words that can be read in a clock cycle at 155.5 MHz is twice the number of physical ports. This is termed “number of equivalent ports”. In any case, even if such a trick would be used, it would not be conveniently implementable; in fact, in that case the required RAM would be 25 Mbit (16×384×64×64×2/2).
A further problem which is connected to the known memory based switch arrangement is the required power, namely energy consumption of the large number of RAMs.
Furthermore, in case of multi chip architecture, a lot of time is needed to provision the whole system because of the sequential configuration through microprocessor. The provisioning through a microprocessor results in a time consuming activity for providing cross connection information. The number of line of software to be written is given by the number of time slots multiplied by the number of output links. Using the above figures, the software lines to be written are 24576 (384×64). The problem becomes even more serious when a multi chip structure is used: in that case, the above number of lines should be multiplied by 4, 8 or more. This time consuming activity renders the matrices hardly scalable.